The combination of 3D silicon stacking and 2.5D packaging technology enables customized computing platforms with revolutionary performance, power and cost.
PALO ALTO, Calif., December 05, 2024 (GLOBE NEWSWIRE) — Broadcom Inc. (NASDAQ: AVGO) today announced the availability of its 3.5D eXtreme Dimension System in Package (XDSiP™) platform technology, enabling customers to consumer AI to develop next-generation personalized accelerators (XPU). The XDSiP 3.5D integrates more than 6000 mm2 silicon and up to 12 high-bandwidth memory (HBM) stacks in a single device to enable high-efficiency, low-power computing for large-scale AI. Broadcom has reached a significant milestone by developing and launching the industry’s first 3.5D Face-to-Face (F2F) XPU.
The immense computing power required for training generative AI models relies on massive clusters of 100,000 scaling up to 1 million XPUs. These XPUs require increasingly sophisticated integration of compute, memory, and I/O capabilities to achieve the necessary performance while minimizing power consumption and costs. Traditional methods such as Moore’s Law and process scaling struggle to meet these requirements. Therefore, advanced system-in-package (SiP) integration becomes crucial for next-generation XPUs. Over the past decade, 2.5D integration, which involves the integration of multiple chipsets up to 2500mm² silicon and HBM modules up to 8 HBMs on an interposer, has proven valuable for development from XPU. However, as new and more complex LLMs are introduced, their training requires 3D silicon stacking for better size, power, and cost. Therefore, 3.5D integration, which combines 3D silicon stacking with 2.5D packaging, is poised to become the technology of choice for next-generation XPUs in the coming decade.
Broadcom’s 3.5D XDSiP platform provides significant improvements in interconnection density and energy efficiency compared to the Face-to-Back (F2B) approach. This innovative F2F stack directly connects the top metal layers of the top and bottom die, providing a dense, reliable connection with minimal electrical interference and exceptional mechanical strength. Broadcom’s 3.5D platform includes an IP and proprietary design flow for efficient patch-by-build 3D chip stacking for power, clock and signal interconnects.
Key Benefits of Broadcom’s XDSiP 3.5D
Improved interconnection density: Achieves 7x higher signal density between stacked chips compared to F2B technology.
Superior energy efficiency: Delivers a 10x reduction in power consumption in die-to-die interfaces using 3D HCB instead of planar die-to-die PHYs.
Reduced latency: Minimizes latency between compute, memory, and I/O components within the 3D stack.
Compact form factor: Allows for smaller interposers and package sizes, resulting in cost savings and improved package warpage.
Broadcom’s flagship 3.5D F2F XPU integrates four compute chips, one I/O chip and six HBM modules, leveraging TSMC’s cutting-edge process nodes and 2.5D CoWoS® packaging technologies. Broadcom’s proprietary design flow and automation methodology, based on industry-standard tools, ensured immediate success despite the immense complexity of the chip. The 3.5D XDSiP demonstrated comprehensive functionality and exceptional performance on critical IP blocks including high-speed SerDes, HBM memory interfaces and die-to-die interconnects. This achievement highlights Broadcom’s expertise in the design and testing of complex 3.5D integrated circuits.
“Advanced packaging is essential for next-generation XPU clusters as we reach the limits of Moore’s Law. Working closely with our customers, we have created an XDSiP 3.5D platform on top of technology and tools from partners TSMC and EDA,” said Frank Ostojic, senior vice president and general manager of the ASIC product division. from Broadcom. “By vertically stacking chip components, Broadcom’s 3.5D platform allows chip designers to combine the appropriate manufacturing processes for each component while reducing interposer and package size, resulting in improvements significant in terms of performance, efficiency and costs. »
“TSMC and Broadcom have worked closely over the past several years to bring together TSMC’s most advanced logic processes and 3D chip stacking technologies with Broadcom’s design expertise,” said Dr. Kevin Zhang, vice-president. Senior President of Business Development and Global Sales and Co-Deputy. COO, Taiwan Semiconductor Manufacturing Company. “We look forward to producing this platform to unlock AI innovations and enable future growth.”
“Through a partnership spanning more than a decade, Fujitsu and Broadcom have successfully commercialized multiple generations of high-performance computing ASICs,” said Naoki Shinjo, senior vice president and head of advanced technology development at Fujitsu. “Broadcom’s latest 3.5D platform enables Fujitsu’s next-generation 2-nanometer Arm processor, FUJITSU-MONAKA, to achieve high performance, low power consumption and lower cost.”
With more than five 3.5D products in development, the majority of Broadcom’s consumer AI customers have adopted the 3.5D XDSiP platform technology and production deliveries will begin in February 2026. For more information on the platform custom 3.5D calculation tool from Broadcom, please click here.
About Broadcom Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies a broad range of semiconductors, enterprise software and security solutions. Broadcom’s industry-leading product portfolio serves critical markets including cloud computing, data center, networking, broadband, wireless, storage, industrial and enterprise software. Our solutions include service provider and enterprise networking and storage, mobile and broadband device connectivity, mainframe, cybersecurity, and private and hybrid cloud infrastructure. Broadcom is a Delaware corporation headquartered in Palo Alto, California. For more information, visit www.broadcom.com.
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