TSMC described its next generation transistor technology this week at IEEE International Meeting on Electronic Devices (IEDM) in San Francisco. The N2, or 2 nanometersThe technology is the semiconductor foundry giant’s first foray into a new transistor architecture, called nanosheet or door all around.
Samsung has a process for making similar devices, and both Intel And TSMC we hope to produce them in 2025.
Compared to TSMC’s most advanced process today, N3 (3 nanometers), the new technology delivers up to 15% speedup or up to 30% greater power efficiency, while increasing density by 15%. .
N2 is “the fruit of more than four years of work” Geoffrey YesTSMC Vice President of R&D and Advanced Technologies told IEDM engineers. Today’s transistor, the FinFEThas a vertical silicon fin at its heart. Nanosheet or full-gate transistors instead have a stack of narrow silicon ribbons.
The difference not only allows for better control of current flow through the device, but it also allows engineers to produce a wider variety of devices, creating wider or narrower nanosheets. FinFETs could only offer this variety by multiplying the number of fins in a device, such as a device with one, two, or three fins. But nanosheets offer designers the possibility of intermediate gradations, such as the equivalent of 1.5 fins or whatever might better suit a particular logic circuit.
Called Nanoflex, TSMC’s technology enables different logic cells built with different nanosheetswidths on the same chip. Logic cells made from narrow devices could make up the overall logic of the chip, while those with wider nanosheets, capable of generating more current and switching faster, would make up the processor cores.
The flexibility of the nanosheet has a particularly big impact on SRAM, the main on-chip memory of a processor. For several generations, this key circuit, composed of 6 transistors, has not shrunk as quickly as other logics. But N2 appears to have broken that trend of stagnation, resulting in what Yeap described as the densest SRAM cell to date: 38 megabits per square millimeter, an 11% increase over the technology previous, N3. N3 only managed a 6% increase over its own predecessor. “SRAM reaps the intrinsic gain of going all the way,” says Yeap.
Future full-gate transistors
While TSMC has delivered details on next year’s transistor, Intel looked at how long the industry might be able to scale back its efforts. Intel’s response: longer than initially expected.
“The architecture of nanosheets actually constitutes the final frontier of transistor architecture” Ashish Agrawala silicon technologist with Intel’s Components Research Group, told engineers. Even the future Complementary FET (CFET) the devices, which could arrive in the mid-2030s, are made of nanosheets. So it’s important for researchers to understand their limitations, Agrawal said.
“We haven’t hit a wall. It’s doable, and here’s the proof… We make a very good transistor. —Sanjay Natarajan, Intel
Intel proved that a transistor with a gate length of 6 nanometers worked well.Intel
Intel explored a critical scaling factor, gate length, which corresponds to the distance spanned by the gate between the source and drain of the transistor. The gate controls the flow of current through the device. Reducing the gate length is essential for reducing the minimum device-to-device distance in standard logic circuits, called contact poly pitch, or CPP, for historical reasons.
“CPP scaling is primarily done based on gate length, but it is expected that this will stop at the gate length of 10 nanometers,” Agrawal said. The idea was that 10 nanometers was such a short gate length that, among other problems, too much current would flow through the device when it was supposed to be turned off.
“So we looked at pushing below 10 nanometers,” Agrawal said. Intel modified the typical gate structure so that the device had only a single nanosheet through which current would flow when the device was turned on.
By thinning this nanosheet and modifying the materials around it, the team was able to produce a device with acceptable performance with a gate length of only 6 nm and a nanosheet only 3 nm thick.
Eventually, researchers expect silicon gate devices to reach a scaling limit, which is why researchers at Intel and elsewhere have been working to replace the silicon in the nanosheet with 2D Semiconductors such as molybdenum disulfide. But the result at 6 nanometers means that those 2D Semiconductors may not be needed for a while.
“We haven’t hit a wall,” says Sanjay Natarajansenior vice president and general manager of technology research at Intel Foundry. “It’s doable, and here’s the proof… We’re making a very good transistor” with a channel length of 6 nanometers.
From the articles on your site
Related articles on the web